The present invention relates, in general, to the field of ferroelectric memories. More particularly, the present invention relates to a reference circuit and method for providing a reference voltage suitable for use with 1T/1C ferroelectric memory architectures.
Ferroelectric memory architectures and reference circuits, such as 1T/1C memory architectures and corresponding reference circuits, are known in the art. An example of a 1T/1C memory architecture is described in U.S. Pat. No. 5,880,989, entitled “Sensing Methodology for a 1T/1C Ferroelectric Memory, assigned to the current assignee, and hereby incorporated in its entirety by this reference. In addition to the 1T/1C memory architecture described therein, at least one reference scheme is shown as well.
One type of ferroelectric reference cell uses one or more charge components of a ferroelectric capacitor as the basis of the reference voltage. The operation of a ferroelectric capacitor is described with reference to the hysteresis FIG. 40 and corresponding voltage diagram shown in FIGS. 1 and 2. FIG. 1 is a plot of the voltage versus charge or polarization of a ferroelectric capacitor. While reference may be made to “charge” in the dielectric of the ferroelectric capacitor, it should be noted that the capacitor charge dissipates, i.e. is volatile. However hysteresis curve 40 also represents polarization, which is non-volatile. Reference is made to both aspects of charge and polarization, which generally correspond before the charge on the capacitor dissipates.
In FIG. 1, the x-axis represents the field voltage applied to the ferroelectric dielectric material of the ferroelectric capacitor and the y-axis represents the polarization vector (or charge) of the ferroelectric material. The flow of current through a ferroelectric capacitor depends on the prior history of the applied voltages. A voltage waveform 47 is shown in FIG. 2 that includes two positive voltage pulses and two negative voltage pulses that are applied to one electrode of a ferroelectric capacitor in a Sawyer tower circuit arrangement, which is well known in the art. The exact timing of the pulses is arbitrary, and can include extremely long pulse widths. Circled point numbers one through six on hysteresis curve 40 correspond to the same circled point numbers on the voltage diagram of FIG. 2.
Starting at a first point 41 on both the hysteresis diagram 40 of FIG. 1 and the voltage diagram 47 of FIG. 2, there is no externally-applied voltage across the ferroelectric capacitor, but there was a previously-applied voltage across the ferroelectric capacitor that left the capacitor polarized at point 41. Applying a positive voltage across the capacitor moves the operating point (i.e., the current polarization) along the hysteresis curve 40 to a second point 42. The change in polarization vector or charge is designated “P” and is labeled on the rising edge of the first voltage pulse shown in FIG. 2 and on the hysteresis curve 40 shown in FIG. 1. The charge liberated with the change in polarization vector is referred to as the “switched charge.” Next, the trailing edge of the first pulse in FIG. 2 occurs between circled numbers 2 and 3. This is typically a return-to-zero transition in the externally applied voltage. Removing such positive voltage moves the polarization along the hysteresis curve to a third point 43. The direction component of spontaneous remnant polarization within the ferroelectric material is unchanged, although there is some loss of field induced polarization, i.e. a loss in the polarization magnitude in a non-ideal ferroelectric material. The change in charge is designated “Pa” and is labeled on the falling edge of the first voltage pulse shown in FIG. 2 and on the hysteresis curve 40 shown in FIG. 1. Circled point 3 is at zero externally-applied volts and, while at zero on the horizontal (voltage) axis, has a non-zero vertical component. Ideally, this remnant polarization ought to remain indefinitely. However, in practice some relaxation may occur. This is shown in FIG. 1. Specifically, between the third and fourth points 43 and 44 on the hysteresis curve 40, there is a “relaxation” of domains within the ferroelectric material resulting in a partial loss of polarization magnitude.
Applying a second positive voltage across the ferroelectric dielectric material moves the operating point from the fourth point 44 on the curve 40 back to the second point 42. The increase in charge is now labeled “U” and is less than the P increase produced by the first positive voltage. Removing the applied positive voltage moves the operating point to the fifth point 45 on the hysteresis curve 40, with a corresponding loss of charge labeled “Ua”.
Applying a negative voltage across the ferroelectric dielectric material at the fifth point 45 on the hysteresis curve 40 moves the operating point to a sixth point 46. The change in charge and polarization is labeled “N” and is shown on the leading edge of the first negative pulse in FIG. 2. The negative voltage reverses the polarization direction of the capacitor, resulting in the original polarization direction. Since the hysteresis curve is substantially symmetrical, removing and reapplying the negative voltage moves the operating point around the “bottom” portion of the hysteresis curve in the same manner as described above. The associated changes in charge around the loop 40 are consecutively labeled “N”, “Na”, “D” and “Da” in FIG. 2. Note that the relaxation of the loop is not shown in the bottom portion of loop 40, though it exists in a non-ideal ferroelectric material, and therefore the charge components labeled “Na” “D” and “Da” are assumed to all be approximately equal. After the two negative voltage pulses are applied and returned to zero applied volts, the operating point is returned to the first point 41 on the hysteresis curve 40.
In prior art reference circuits, the reference voltage, bit line voltage for switching, and bit line voltage for non-switching are generally associated with the Da, P, and U charge components of hysteresis loop 40 shown in FIG. 1, respectively. These three charge components have different temperature and voltage coefficients. In general, as temperature increases, the P component decreases and the U and Da components increase. When the memory operating voltage (VDD) increases, all three components increase, but the P component increases the most. Since the Da component is smaller than the U component, a much larger reference capacitor is needed to place the reference voltage above the bit line voltage for non-switching and below the bit line voltage for switching. The ratio of the capacitor size of the reference cell to the capacitor size of the memory cell is called the “scaling factor”. As discussed, the scaling factor should be much be larger than one. It is desirably in the range of 1.5 to 5.0, depending on the circuit design. This scaling factor amplifies the temperature and voltage coefficient of the reference voltage. Therefore, in prior art designs, the reference voltage selection is limited to a reduced range in order for memory parts to work at a low temperature and low voltage and a high temperature and high voltage. In other words, the loss of a certain amount of signal margin is the cost for using these prior art reference circuits.
One of the long time reliability issues for ferroelectric reference circuits and ferroelectric memories in general is imprint. Imprint causes the opposite state P component to decrease and the opposite state U component to increase. Therefore, imprint effectively reduces the signal margin. Since the prior art reference circuits also cost signal margin, the opposite state retention time is also reduced.
In prior art reference circuits, when a memory cell on a column is accessed, the reference cell is also accessed. Therefore, reference cells bear a much higher electrical stress than do the memory cells. A more stable component in reference cells is thus needed. The reason that the Da charge component is used in the prior art reference circuits is based on a fact that Da does not fatigue. However, the ferroelectric memory cells use the “P” and “U” terms, which do have the potential of fatigue.
If, on the other hand, a reference is constructed that uses the P and U terms in order to track the memory cells, then the reference cell capacitor will fatigue, and the memory part will prematurely fail. Therefore, reference circuits that use the P and U terms, but have a reference capacitor that is accessed every time that a memory cell on the same column or same row is accessed, are not ideal for a commercial ferroelectric memory.
Another disadvantage in prior art reference circuits is that the optimized number of reference capacitors (or the size of reference capacitors, or the scaling factor) might be different from lot to lot. Additional cost is required to determine the optimized reference for each lot.
What is desired, therefore, is a reference circuit for a ferroelectric memory that accurately tracks the charge components of a ferroelectric memory cell so that voltage and temperature performance is optimized, but that does not fatigue resulting in premature failure of the ferroelectric memory.